IBM and Samsung Electronics have introduced a new semiconductor design – the Vertical transfer field effect transistor (VFT) architecture.
The companies announced on Dec. 15 that the new semiconductor design could potentially reduce energy use by 85 percent compared to a scaled fin field-effect transistor (finFET). Samsung Electronics also announced plans to produce IBM5 nanochips for servers.
VTFET technology addresses many performance barriers and limitations to extend Moore’s Law as chip designers try to fit more transistors into a fixed space.
According to IBM and Samsung, this design has two advantages. They estimate that VTFET will make processors twice as fast, or 85 percent less powerful, than chips designed with FinFET transistors.
IBM and Samsung, which have not said when they plan to commercialize the design, are not the only companies trying to go beyond the 1-nanometer barrier.
During the conversation, IBM and Samsung explained how to change circuits from horizontal to vertical, while making semiconductor chips with smaller footprint more powerful and efficient.
However, as processes approach the atomic limit, the semiconductor industry is actively moving in a vertical direction.
The breakthrough structure will allow transistors with vertical current flow to be embedded on chips, resulting in more compact devices and paving the way for smartphones to operate over long periods.
In essence, the new design will use vertically stacked transistors to allow current to flow up and down the transistor stack rather than the left-right horizontal layout used by most chips.
According to IBM, the new vertical structure allows more transistors to be fitted in space. The company says the design could potentially double performance or reduce energy consumption by 85%.
IBM produced test chips with this new VTFET architecture and envisioned it as a game changer in many areas. As the Internet of Things grows, these chips could enable devices such as ocean buoys and self-driving cars to run on less energy, and could have a similar impact on cryptocurrency mining and other energy-intensive computing processes, reducing their carbon footprint.
WCCFTech notes that research teams at IBM and Samsung have described how to change the crystal pipeline architecture, inspired by groove-based DRAM longitudinal crystal-tube storage.
The 3D vertical device design solution enables chip manufacturers to continue in the direction of Moore’s Law after determining the “determining gate/transistor distance” of two key factors, such as gate length and spacer size.
At the recent 2021IEEE International Conference on Electronic Devices IEDM, Intel introduced key technologies in packaging, transistors and quantum physics, outlining its future technological development directions.
IBM and Samsung use VTFET technology to show people CMOS semiconductor designs and potentially explore scaling performance beyond nano. IBM flexed its muscles in semiconductors again this year when it announced it would build the world’s first chip with a 2nm process node.
As transistors, the basic building blocks of computer chips, get smaller and smaller, chips become faster and more energy-efficient.
On the evening of May 6, IBM announced an important breakthrough in its semiconductor design and process: the world’s first chip using 2nm process technology will help advance the semiconductor industry. IBM’s 2nm chips are expected to deliver 45% more performance and 75% less energy than the current mainstream 7nm chips.
The latter has been upgraded from FinFET to nanosheet technology, which allows for better customization of the voltage characteristics of individual transistors.
For example, it can enhance the capabilities of cutting-edge workloads like AI and cloud computing and explore new ways to enforce security and encryption on hardware by injecting core-level innovations.
Gate-all-round/Nanocase/Wraparound Gate technology transistors are key to how transistors are manufactured in the new process, although IBM did not explicitly state that this new 2nm processor uses a 3-Stack GAA design.
By contrast, Intel could introduce some form of GAA on its 5nm process.
Importantly, all key functions of IBM’s chip will be etched using EUV lithography.
IBM and Samsung have not said when they plan to commercialize it.
The 3nm process is split into two versions, with the 3GAE “low power” version going into production in early 2022 and the 3GAP high-performance version going into mass production in early 2023.
All I know is that it’s still GAA transistors, based on MBCFET “multi-bridge channel FT” technology (e.g. 3nm), which is a nanosheet transistor that stacks vertically and is compatible with current CMOS processes, sharing equipment and manufacturing methods to reduce upgrade costs for new technologies.
Unlike existing 2nm technology, which IBM has previously launched globally, the chip, which can integrate 50 billion transistors in the size of a fingernail, is expected to be ready for production by 2020, with a performance improvement of 45% or a 75% reduction in power consumption over the 7nm process.
According to them, the chip has a density of 333 million transistors per square millimeter. 44nm contact multi-pitch + CPP with gate length of 12nm; Based on IBM’s ongoing use of horizontal nanosheet (IDHS) cross-sections, GateAll Impact ++ can perform GAA using a variety of methods; Compared to the state of the art 7nm chip, the performance is improved by 45% and power consumption is reduced by 75%.
The new process will produce about 50 billion transistors on chips the size of a fingernail, IBM said in a press release. It will also deliver efficiencies 75 percent higher or 45 percent faster than today’s 7-nanometer chips.
Over the past few decades, nanonomenclature has indeed matched the size of certain chip components.
This is the successor to FinFET, the 3D transistor technology widely used by major fabs.
Importantly, all key functions of the IBM chip will be etched using EUV lithography.
To put that in perspective, IBM’s 2nm chip has a transistor density of 333 million transistors per square millimeter (MTr/mm).
It is worth mentioning that the 2nm here is not the physical 2nm, but the equivalent node “EaseNodes”, where the next generation process evolves from the 5nm and 3nm technologies. Code “.
However, IBM overcame the problem by using extreme ultraviolet lithography (EUV) to draw the front end of the line, which greatly promoted the commercialization of EUV.
That compares with about 171 million transistors in TSMC’s current 5nm chip and about 127 million transistors per square millimeter in Samsung’s 5nm process. IBM can make chips smaller, faster, reliable and efficient by increasing the number of transistors on each chip. The success of the NM chip process design meant that it took less than four years for IBM to achieve another technological breakthrough after announcing the design and development of five nanometers.
Currently, only TSMC chip makers in the world are able to break through the ability of advanced process technology below 10nm. As chip manufacturing approaches the physical limits of Moore’s law, it becomes increasingly difficult to develop.
Although the current semiconductor space seems to be in trouble, with advanced manufacturing processes often having problems, IBM has now successfully developed 2nm chip processes.
As the process evolves, the number of companies capable of manufacturing advanced node chips is shrinking.